1. Field of the Invention
The present invention relates generally to integrated circuit (IC) memories and more particularly, to a NOR-type ROM with hierarchical-BL structure, dynamic segmentation shielding, and source programming.
2. Description of the Related Art
Read only memory (ROM), which have nonvolatile, high reliability, small area, high speed, and high compatibility, are commonly embedded in system on chips (SOCs) for storing a large number of fixed programs and data.
In recent years, there are three kinds of mask-programming ROM bit cell as recited below.
1. Filed Oxide Programming:
Such programming is applicable to NOR-type logic cell array for identifying whether an N-type metal-oxide-semiconductor (NMOS) field-effect transistor is produced in the process of oxidation of the substrate to serve as the manner of data recognition, providing higher operating speed in performance. Referring to FIG. 1, the black solid line 101 indicates a normal NMOS for providing discharging path to serve as data 0. On the contrary, the black dotted line 102 indicates none of any NMOS to serve as data 1. However, the mask programming belongs to the front-end engineering to be caught up with the manufacturing process too much, so the response time is longer and the regeneration rate is worse. In FIG. 1, WL denotes word line and BL denotes bit line.
2. Implantation Programming:
In such programming, the steps of the ion implantation process are doped with different concentrations or materials to result in change of the threshold voltage of the NMOS to further make the depletion-mode/enhancement-mode NMOS or the high-threshold-voltage/low-threshold-voltage NMOS to serve as the bitcell programming, wherein the high-threshold-voltage/low-threshold-voltage NMOS is preferably applicable to the NOR-type structure and the depletion-mode/enhancement-mode NMOS is preferably applicable to the NAND-type structure. Referring to FIG. 2, when the gate is low-voltage, the depletion-mode NMOS 201 will produce a channel for the bit line (BL) to discharge and meanwhile, the code-pattern is zero (0); in the meantime, the enhancement-mode NMOS 202 will cut off the channel to keep high and meanwhile, the code-pattern is one (1) for NAND programming. Such programming can produce flat cells without any contact to have better area benefit but to lose some speed and not all of manufacturing processes of standard complementary metal oxide semiconductor (CMOS) are supported.
3. Contact/Via/Metal Programming:
Such programming is based on the contact, via, or metal to determine whether the cell is connected to the BL for providing discharging path for the purpose of code-pattern and the operating speed is higher due to more current gain. In the circuit shown in FIG. 3(A) and the circuit layout shown in FIG. 3(B), a cell having a via between the BL and the NMOS is denoted by 301 and the other cell having no via is denoted by 302, wherein the two cells share one terminal (source) for grounding. However, encoding space must be reserved to the source and the source cannot be shared by other NMOSs, so the bit density is slightly higher. In cycle time of such programming, modifying mask approaches ultimate engineering, so the turn around time (TAT) is the shortest and the regeneration rate is highest to lead to optimal time to market. Thus, such programming is the mainstream of programming of the contemporary mask ROM.
As the manufacturing process develops, the interval between the BLs becomes shorter and the noise problem resulting from crosstalk has become non-ignorable. In recent years, crosstalk induce read failure (CIRF) has become attentive for some of memory structures to be studied and improved. Among the improved memory structures, three typical ones are recited below.
1. Dynamic Virtual Guardian (DVG) Technique:
Referring to FIG. 4(A), two of six clamped NMOSs 401-406 are put into each BL and controlled via column select signals. When BL[n] is selected, the column select signal activates the NMOS 407 for transmitting the signal to the sense amplifier SA and activates the clamped NMOSs 403,406 located at two sides adjacent to the BL for making oscillations of the voltage at the two sides be held back by the clamped NMOSs under a high voltage to suppress coupled voltage drop to the BL. However, it is necessary to insert the clamped NMOSs additionally, so the required area is larger. Besides, direct current (DC) path is likely generated between the clamped NMOSs and the bitcell to result in a great amount of DC power consumption and to cause that the crosstalk holdback effect is deteriorated by logic intensity.
2. Content-Aware Design Framework:
Referring to FIG. 4(B), each BL is constituted by hierarchical segmentation framework. Column-oriented encoding based on algorithm and local BL switches (LBS) are applied to determine whether all are jointly connected to the BL to equalize the parasitic capacitance on each BL and to secure that self-capacitance suffices to hold back the interference resulting from the crosstalk. Besides, such framework needs a special algorithm, such as Code-structure Programming Algorithm, and the circuit also needs (1) a hybrid-segmented BL 432, (2) flag table 633, and (3) dual-path output drivers 634 to lower occurrence of excessive code-patterns of zero (0) so as to equalize the parasitic capacitance on the BL to further decrease the influence of the crosstalk. Such framework though can reduce the BL loading, but complicated code algorithm is needed to make the programming more difficult and it is necessary to additionally include the flag table and dual-path output drivers to lead to area penalty and power penalty. Besides, equalizing the parasitic capacitance can only reduce the degree of influence caused by the crosstalk and noise on the BL and cannot fully prohibit the crosstalk, so sensing margin can still be partially lost under low-voltage environment to further lower the immunity against the noise.
3. Dynamic Split Source Line (DSSL):
DSSL is an NAND-type ROM framework which is operable under the low-voltage (0.29V) environment and the working frequency of which can reach 3 MHz. As shown in FIG. 4(C), how the circuit of source is connected is done by odd and even and works with column address least significant bit (LSB) SL_sel 441 for control of source supplementary switch and for only providing discharging path for the source of strings, bits of which are accessed, where the adjacent BLs and sources of other strings are connected to high potential, thus solving the problems of crosstalk interference and current leakage. However, the access current of such framework, so low-voltage operating speed is quite limited. Besides, when the ROM capacity is increased, the number of cells that the LSB 441 is connected with at row direction increases, and NMOS of a source line (SL) driver needs to be very large to avoid bottleneck of access performance, thus bringing forth considerable additional area and power penalties.
As known from the above, none of any ROM framework having high stability and high speed without additional area penalty under low-voltage operation has been available to date.
The conventional ROM framework cannot be operated under low voltage, loses speed or stability under low-voltage operation or needs to pay additional area penalty.